Simulation of a processor for multiplying binary numbers
In paragraph 4.4, general principles for constructing processor devices are considered, a logical scheme of an operational machine for multiplying binary numbers (see Figure 4.23), as well as circuits of control automata with a circuit (see Figures 4.26 and 4.28) and programmable (see (see Figures 4.29, 4.33 and 4.34) with the logic. The purpose of this paragraph is to create separate nodes and a processor device in general, using the Micro-Logic II software package, to check their operability and to reveal the features of the operation. In Section 4.4, two algorithms are considered (see Figure 4.25) for the processor implementation of the multiplication operation. For modeling, a processor with multiplication by algorithm 2 is selected.
An operating machine for multiplying binary numbers
Schematic features of the operating machine
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The scheme of the operating machine (Fig. 13.23, a) is constructed using the Micro-Logic II library elements according to the principles described in Section 4.1, and in contrast to the circuit in Fig. 4.23 contains the timing (SI) and start pulse (PI) circuits.
The structure of the operating machine includes:
• registers RG 2 and RG 3 for storing partial products, which use the chips of the four-digit register K155IP1 (library macronutrients 95). The low-order output P4 of the register RG 3 is connected to the serial input of the register RG 2. Therefore, RG 3 and RG 2 form an 8-bit shift register, from the outputs P7, ..., P0 of which partial products and the final result (product) are removed. On the parallel inputs of the data B 3 , B 2 , B v B 0 of the register RG 2 the factor B = 0101 is applied. The low bit P0 of the register RG 2 is used as the logic condition X1. Parallel inputs of the register RG 3 are connected to the outputs of the four logic elements I. A 0 is input to the serial input RG 3;
• the subtracting counter CT, performed on the K155IE chip 7 (library macrocell 193). Data inputs D 3 , D 2 , D v D 0 of the counter CT operand 0100 (number 4) is applied to fix the end of the multiplication operation, to the reset input R - logical level 0 (the counter is ready for operation). To generate the logical condition X2 = 1 about the end of the multiplication operation (zero signals on the output of the counter), the ZILI-NOT element is used;
• the summator SUM, assembled in a sequential scheme of four single-digit totalizers (library macro-cell SM SC). The inputs A y A 2 , A v A 0 of the adder SUM is given a multiplier A = 0111. Four others inputs of the adder are connected to the outputs P v P 0 , P 5 , P 4 registers RG 3, and the outputs of the adder - with the inputs of the AND gates
• logical elements designed to ensure the normal operation of the operating machine;
• the signal generators D 0i - D 05 for the formation of the trigger pulse (PI), the sync pulse (SI) and the sequence of microinstructions V, Y 2, F3, required for multiplying the binary four-digit numbers 0111 and 0101.
Fig. 13.23. Scheme of an operation machine for multiplying binary numbers (a) and time diagrams explaining the principle of its operation (b)
The register RG i (see Figure 4.22), in which the constant A = A 3 A 2 A is permanently stored i A 0 = 0111, into the one shown in Fig. 13.23, a the circuit is not included, because the digits A 3 = 0, A2 = I1A1 = IjA0 = I of the multiplier are directly applied to the inputs of the adder < i> SUM.
Thus, the multipliers A = 0111 are supplied to the inputs A3, A2, A1, A0 of the adder; to the parallel inputs of the data B 3 , B v B i , B 0 of the register RG 2 - the operand B = 0101, and the serial input is a logical 0; to the data inputs D 3 , D 2 , D v D 0 of the counter CT - operand 0100 (number 4), to the reset input R - logical 0.
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