FPGA I/O Units
These blocks usually contain two channels - for inputting signals and for output (Figure 4.36), which are connected to the same pin pad of the chip.
In each channel, signals can be transmitted directly between the pad and the FPGA input/output. For this, the upper inputs of the multiplexers are used. In addition, the signals can be fixed in flip-flops, and in this case they come through the lower inputs of the multiplexers.
Fig. 4.36. FPGA I/O Block
The output amplifier of the FPGA can be transferred to the third state, with the output pin of the microcircuit being open. As is known, on the open contacts in the CMOS devices there is accumulation of a charge, which leads to the appearance of false signals. To prevent this from happening, the chip provides for the connection of the contact pad through the resistors either to a high voltage level or to a zero point (housing). This function is performed by two transistor switches. The choice of this or that key is carried out during programming.
FPGA interconnect systems
The links in the FPGA are composed of relatively short sections that do not contain keys - segments. They can be of different lengths, vertical and horizontal. Segments with each other can be connected using keys, closed during programming. A small number of segments leads to ineffective use of LB, too large - to the emergence of a large number of programmable. Short segments make it difficult to realize long ties, and long ones make short ones. Therefore, a system of connections with several types of interconnections, both long and short, is advisable for transmissions at different distances.
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The Actel role is played by the antifuse in the development of FPGAs with a single programming based on jumpers antifuse in the FPGA of this company are arranged in the form of horizontal rows, between which there are trace channels (Figure 4.37).
Fig. 4.37. The FPGA interconnection system of the company Aciei
In a horizontal channel, four segments contain segments of different lengths. They are crossed by vertical segments. At the intersection of the vertical and horizontal segments, there are programmable antifuse jumpers that allow you to connect vertical and horizontal segments. In Fig. 4.37 they are indicated by circles.
Each LB has one output and four inputs, two of which are located at the top of the LB, and two - at the bottom. Each of the LB inputs is connected to one of the short vertical segments, with the upper LB inputs connected to the vertical segments located in the upper row, and the lower inputs to the segments in the bottom row. The output of each LB is connected to its own vertical segment, intersecting several horizontal channels at once. Thus, to connect the output of one LB to one of the inputs of another nearby LB, it is sufficient to close two jumpers: a bridge connecting the vertical segment of the LB output to the horizontal one, and a bridge at the intersection of this horizontal segment with the corresponding vertical entry segment.
If LBs whose output and input need to be connected are not located in the same column, there are special programmable keys that allow you to connect the ends of the horizontal segments to each other. Thus, you can increase the length of horizontal links.
In addition to the vertical segments of LB inputs and outputs in the vertical directions, there are also additional segments intersecting several rows of LB and tracing channels. Each such vertical segment can connect to the horizontal segments that it crosses. These segments can be connected to the outputs of neighboring LBs.
In horizontal channels there are continuous segments along the entire length, which are connected at one end to either the supply voltage or the housing. With the help of such segments, log signals can be fed to the LB. 1 and 0.
Thus, the switching system contains a set of segments for various purposes and means of their switching, which provides a wide variety of options for connecting LBs to each other.
To program a jumper, i.e. close it, it should be applied to increased voltage U pr. Since the jumpers are located at the intersection of rows and columns, one of these lines is energized U pr, and the other is grounded. In order for the remaining jumpers to remain intact, before that, all segments of the chip are charged to the level U np / 2. Thus, when applying voltage U to one of the lines, and on the other - & quot; 0 & quot; Only one jumper located at their intersection will fall under the voltage U pr, all the others will fall under the voltage U pr/2, not breaking through the jumper.
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