Control automaton with circuit logic (UASL), Appointment and composition of UFSL, Principle of work of UFSL - Informatics

Control automaton with circuit logic (UFSL)

Purpose and composition of the UFSL

The control automaton serves to form a sequence of microinstructions from a given set of Y1, Y2, Y3 using logic signals X1, X2 coming from the outputs of the operating machine. The sequence of microinstructions generated by the control automaton arrives at the inputs of the operating machine and ensures the operation of multiplying binary numbers.

The principles of constructing UFSL are set out in paragraph 4.4. Its composition (Figure 13.24, a) includes a combinational circuit and two RS-flip-flop designed to store signals about the state (a n ) operating machine. It has two information inputs X1, X2 and two control inputs, to which the sync pulse SI and the trigger pulse of the UI for resetting the triggers arrive.

How OSF works

At X2 = 0, depending on the state of the information input X1 on the slice of each incoming sync pulse, the control automaton forms one of the microinstructions Y1, Y, or Y3 (Fig. 13.24, b). Regardless of the state Inputs X v X 2 of the control automaton, the starting pulse PI = 1 triggers the reset of the triggers. Therefore, the code of 00 comes to the input of the decoder and one signal is formed at one of its outputs, corresponding to the initial state a 0 or the microcommand Y1. On the cutoff of the first SI (after the UI), the registers and the counter of the operating machine are initially loaded. After the initial loading of X 2 = 0, therefore:

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• For X1 = 0, on the slice of each subsequent SI, the control automaton generates a Y3 shift microcontrol of the contents of the register pair RG 3 , RG 2

• At X1 = 1, on the cutoff of the first sync pulse SI, the microinstruction Y2 of the addition of the contents RG 3 and RG1 is formed, and on the slice of the next SI - microcommand Y3 of the shift of the contents of the register pair RG 3 , RG 2.

Control automaton with circuit logic (a) and time diagrams explaining the principle of its operation (b)

Fig. 13.24. Control automaton with schematic logic (a) and timing diagrams explaining how it works (b)

With the input of the signal X2 = 1 the multiplication operation is completed.

Testing the functioning of ACJI. Four generators D01 to D03 are used to test the operation of the UASL. The generators D01, D02 generate input signals X1, X2; generator D03 - sync pulses; generator D04 - starting pulse PI = 1 at the first clock cycle. We select the signals X1, X2 (Table 13.2), starting from the algorithm for multiplying the binary numbers 0111 X 0101 (see Figure 4.21). In this case, UFSL should generate the following sequence of microinstructions: Y i → Y 2 → Y3 - & gt; Y 3 → Y 2 → F3 F3, → The end of the multiplication operation (X2 = I).

Table 13.2

So

you

0.1

2.3

4.5

6.7

8.9

10, 11

12, 13

14

χ

0

I

0

0

1

0

0

0

Χ Ί

0

0

0

0

0

0

0

1

MK

F1

Download

Y 2

Addition

Y 3

Shift

Y 3

Shift

Y 2

Addition

F3

Shift

Y 3

Shift

End

As it is clear from the time diagrams (Figure 13.24, b), it is this sequence of microinstructions that was obtained as a result of modeling the UFSL scheme.

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