DFT is a method that provides certain testability features to the design making an IC more testable. DFT approach improves the controllability and observability of interior nodes, so that embedded functions can be examined easily. Two basic properties determine the testability of any node: 1) controllability, which really is a measure of the issue of setting internal circuit nodes to 0 or 1 by assigning ideals to main inputs (PIs), and 2) observability, which is a measure of the difficulty of propagating a node's value to a primary end result (POs). A node is reported to be testable if it is easily controlled and noticed. DFT is also a measure of how easy it is to create test models having high mistake coverage and can be explained as the ability to generate, evaluate, and apply assessments to boost quality and decrease test time and test cost. DFT has an expense benefits in both product validation and developing process.
1. 2 Present day circumstance of the DFT in the Industries
DFT is a leading method utilized by all the Chip Execution Industries to locate and analyze the faults before the fabrication of any sort of chips. The main benefit of this DFT is all the faults are diagnosed and diagnosed prior to the fabrication of the chip which makes the chip execution easier based on the required specs and reduces life circuit cost, wastage of resources etc.
1. 3 Motivation to get this done project
In past, tests of sophisticated design before or after the hardware fabrication with only main ports has become a difficult task. This poses many new design difficulties in neuro-scientific testing. Controlling the internal nodes of the look using only key IO's is becoming complicated. To get over this, DFT technique is introduced before the fabrication of chip which provides controllability and observability to all the nodes in the design through scan chains with insight and output plug-ins at the gate level. Faults that are present anywhere in the design can be recognized and diagnosed. Further Timing evaluation is performed at IP and top level to validate all possible timing pathways with timing constraints for just about any timing violations.
1. 4 Objective of the job work
The objective of the job is to put into action the DFT technique for DUT to increase the test coverage without increasing the test cost during tests of chip at gate level. This DFT strategy includes scan insertion and compression for DUT. Further Static Timing Examination ( STA ) is done for DFT inserted DUT to fix all timing violations. Formal confirmation is done between two variants of design (RTL-RTL, RTL-Netlist, Netlist-Netlist) for reasonable equivalence check.
1. 5 Project Work Schedule
Ramp up. .
Scan Insertion for DUT.
1. 6 Company of the task report
This article is a guide for the work done in this project. The First section is a short introduction which includes mainly purpose and Time plan of the task. The second chapter discusses about the Books review and Record theory of the task. The third section contains methodology followed to put into practice the task. The fourth section elaborates on the results obtained and inference of the results. The Fifth chapter requires to the conclusions and future opportunity of the project
This section includes the next topics
Introduction to DFT
Types of Faults
2. 1 Benefits to DFT
DFT refers to the design techniques that make the duty of subsequent trials easier. There is obviously no single methodology that solves all embedded system-testing problems. There also is no single DFT technique, which is effective for all sorts of circuits. DFT techniques can categorized into two categories
In this method large designs are partioned to small design to lessen the test cost and test details are added by hand to the designs to increase testability and observability. The controllable tips (cp) are energetic tips and observable things (op) are passive ones.
Fig 2. 1. Ad-hoc method - Test point insertion
Experts are needed and test era is often manual
No assurance of end result ( poor problem coverage)
Increase design iter