Control automaton with programmable logic (UAPL)...

Control automaton with programmable logic (UAD)

The purpose and composition of the UAPL

The control automaton must generate the sequence of microinstructions F1, F2, F3 required for the operating machine based on the logic condition signals X1, X2 coming from the operating machine. It consists of a memory node (in the form of a combination scheme - see Figure 4.33) and a microprogram control unit (BMU - see Figure 4.34), which are discussed in detail in paragraph 4.4. Here are the circuit features of these nodes, performed by means of Micro-Logic II for simulation of processes in the UPLF, and the results of checking their functioning.

Node of memory

For the operating machine in question, six microinstructions should be stored in memory. In addition to the 3-bit address, each micro-program micro-program contains a 3-bit field of transition conditions and a 3-bit field of micro-commands for controlling the operating machine. Thus, it is necessary to store six 9-bit micro-commands.

The simulated circuit is shown in Fig. 13.25, a and differs from the scheme shown in Fig. 4.33, the presence of two

Memory of the firmware in the form of a combination scheme (a) and time diagrams explaining the principle of its operation (b)

Fig. 13.25. Firmware memory in the form of a combination scheme (a) and timing diagrams explaining its operation (b)

buffers in the chains ΠXt and ILX2. The circuit has three address inputs AD 0 ', AD ', AD 2 ', to which the modified address arrives from the microprogram control unit. From its output, a 9-bit microprogram micro-program is removed (see Table 4.14 - Algorithm 2), containing the three-digit address (AD0, AD1, AD2) indicated in the firmware, logical conditions checking signals (Π, ПХ2, IlX1) and microinstructions (Y1 , Y2, Y3).

Verifying the efficiency of the combinational scheme consists in sending 3-bit addresses AD2 ', AD1', AD0 'to its input and receiving 9-bit data at the output. The check showed that the memory node performs its functions, since the output data coincides with the micro-commands of the microprogram shown in Table. 4.14 (algorithm 2). For example, from Fig. 13.25, b it is clear that in the interval 3 the address code AD 0 '= 010, and 9-bit data 100101000 is removed from the output, which coincide with line 3 for the MKZ table. 4.14. Note that intervals 4, 7 and 8 should not be taken into account, since they reflect memory cells that do not contain micro-commands.

In the microprogram control block diagram (Figure 13.26, a) the T triggers are executed on JK - triggers, and for

Block of microprogram control (a) and time diagrams explaining the principle of its operation (b)

Fig. 13.26. The firmware block (a) and the timing diagrams explaining its operation (b)

of the normal functioning of the unit, delay elements D 20 and three D-flip-flops are introduced. In BMU, you can select three address channels and a control node. Each address channel contains:

• JK-trigger with asynchronous RS - inputs to load bits (AD0, AD1, AD2) of the address;

• two 2N-NOT elements, controlled by synchro-pulses of SI. At SI = 0, the logical elements are opened and the address bits are entered in the JK -trigger; when S1 = 1 JK , the trigger is converted to a countable mode, since S = R 1 = and J = K 1? =

• D-trigger for temporarily storing the address bit.

The control node consists of the logical elements 2I-2I- OR and 3I. When SI = I, П = 1, it generates a signal T = 1 if one of the following conditions is fulfilled: IlX1 ■ X1 = 1 or IIX1 ∙ X2 = 1, where P is a signal that initiates checking of logical conditions; IIX1, ПХ2 - single signals indicating the condition under which the verification takes place; X1, X2 - signals informing about the fulfillment or non-fulfillment of logical conditions (come from the operating machine). For simplicity, Fig. 13.26, a only the verification of logical condition X1 is reflected, therefore zero signals are fed to the outputs of the lower AND gate of the 2-OR gate.

If the signal T = 1 is generated, then the contents of the counter made up of JK -triggers are incremented by 1, therefore, the address is modified.

Two inverters and D20 delay elements can be assigned to the control node, enabling the counter to operate on JK - triggers and loading D-flip-flops with the required delay.

When checking the functioning of the BMU its inputs were supplied with a permanent address code AD2AD1AD0 = 011, corresponding to the microcommand for checking the logical condition X1. We considered 8 combinations of signals Π, HX1, X1, with the signal Π = 1 at the intervals 0-8 and Π = 0 at the intervals 9-18. As a result of the verification, it was revealed that with the combination Π = IIX1 = X. = 1, the output address is AD 2 AD i 0 = AD2AD1AD0 + 1 = 0100. For all other combinations, the input address code remained unchanged, i.e. AD 2 AD i AD 0 = AD2AD1AD0 + 1 = 011.

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