# Counters, Binary counters, Decimal counter - Computer science

## Counters

The principles of construction and operation of counters are discussed in detail in Section 3.9, so we will confine ourselves to a brief exposition of the results of modeling.

## Binary counters

In Fig. 13.20 shows the scheme of a 4-bit binary asynchronous counter on JK - flip-flops (c) and time diagrams (b), explaining the principle of its operation. All triggers work in counting mode, since the information inputs have the signals J = K = I. In the above diagram, each subsequent trigger is triggered by a signal from the direct output of the previous one.

In the time interval 0 from the output of the signal source D01, a reset signal R = 0 is applied, setting zero counter values ​​on the direct outputs of the counter triggers. Counting pulses are fed from the output of the generator H_1. The change in the state of the counter occurs by the slice of the pulses. When using the counter outputs as triggers, the contents of the counter is incremented by one with the arrival of each pulse (the top row of numbers under the time diagrams). If, for indications, inverse signals are selected, then the counter content decreases by one with the arrival of each pulse (the bottom row of numbers under the time diagrams). From the time diagrams you can see the cyclic nature of the counter operation. After the 15th pulse, the counter returns to its original state. Fig. 13.20. Scheme of a 4-bit binary counter on JK -triggers (a) and time charts (b), explaining the principle of his work

In Fig. Figure 13.21 shows the circuit of a 4-bit binary asynchronous counter on D flip-flops (c) and time diagrams (b) of its operation. In the above diagram, each subsequent trigger is also triggered by a signal from the direct output of the previous flip-flop. However, when reading the counter from the direct outputs of the triggers, its content Q3Q2Q1Q0 decreases by one with the arrival of each pulse (the top row of numbers under the time diagrams). Therefore, at the 0th time interval, the signal S = 0 is fed from the output of the signal source D01, setting single signal values ​​on the direct outputs of the counter triggers. When the signals from the inverse trigger outputs are removed, the device becomes a summing counter. These features are caused by the fact that the counter uses triggers whose state changes along the edge of the control pulses. Fig. 13.21. Scheme of a 4-bit binary counter on D-flip-flops (a) and timing diagrams (b), explaining the principle of its operation

## Decimal Counter

In Fig. Figure 13.22 shows the scheme of one decade of the binary decimal counter on the JK -tiggers (a) and the time diagrams (b), its conversion factor is 10, since after the tenth pulse all triggers are reset the pulse coming from the output of the 2-NOR gate. Fig. 13.22. Scheme of a single-digit decimal counter for JK -triggers (a) and time diagrams (b) explaining the principle his work

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