Hardware of modern processors, Cache memory, Interface tools - Informatics

Hardware of modern processors

Consider the basic hardware of superscalar processors - command and data processing facilities, as well as command execution facilities.

Cache memory

To speed up processor access to main memory, a high-speed buffer memory is placed between them, called cache (simply cache). In modern universal processors, up to three levels of internal command and data cache, which significantly improves the performance of the processor by accessing commands and data with the processor clock speed (gigahertz units); due to a significant reduction in the number of accesses to external memory, which are performed with a lower system bus frequency (tens of megahertz).

The cache module contains a memory management device and a Translation Lookaside Buffer (TLB), which converts the address of the external memory cell to the appropriate address for accessing the cache. The base addresses of the memory pages of commands and data to which the last calls were executed are written to the TLB buffer. When accessing them, their base addresses are read from the buffer, which speeds up the formation of the physical address.

Interface Tools

The processor communicates with the main memory and external devices via a system bus (trunk) consisting of individual address, data and control buses. The data bus is bi-directional. It sends commands (instructions) to the processor and exchanges data with the main memory and external devices. The width of the bus for 32-bit processors is 64 bits, which increases the intensity of data exchange. To implement the protocols of exchange with the system bus in the processors there is a bus interface unit (Bus Interface Unit - BIU). The BIU provides output and reception:

• the necessary signals for managing the exchange, performing interrupts, capturing buses, snooping (calling the external device to the internal data cache) and setting the initial state (signal RESET);

• Parity bits, which control the errors of access to the bus for each byte of the address and data.

With some technical solutions, the processors use an external cache memory of the second level, executed on a separate chip, but located in the same casing with the processor. To exchange data between the processor and the external cache, a separate cache bus (double independent DIB bus architecture) is provided. The interface means of such processors contain additional controllers that support the required communication protocols.

To order the calls to the system bus and the second level cache, additional interface tools such as the Memory Order Buffer (MOB) can be used.

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