Multibit binary adder
The adder of this class performs the addition operation of two operands, each of which is an nbit binary number. Two types of adders are used: sequential and parallel transfer combiners.
Totalizers with sequential transfer
In order to calculate the sum of two nbit binary numbers, you can use incomplete and complete singledigit adder. In Fig. 4.4, a, b the scheme of the 4bit adder and its symbol are given. The circuit is made up of four complete singledigit MS totalizers by connecting
Fig. 4.3. Minimizing the structure of the formula for the total adder (a) and its logical schemes (b, c)
the output of the transfer of the previous onedigit adder with the transfer input of the subsequent one. Such an adder is called a adder with sequential carry. Using a zerobit full onebit adder extends the functionality of the 4bit adder. The adder with sequential transfer has a low speed, since the sum signals S j
Fig. 4.4. The scheme of a 4bit adder with sequential transfer (a) and its symbol (b)
and carry C {+, at the output of the ith singledigit adder appear after the transfer signal is generated in the previous ( i  1) th singledigit adder.
Totalizers with parallel transport
Let's consider a way of increase of speed on an example of a 4bit adder. To do this, we write the output transfer signal (4.3) in the form
(4.5)
where
It follows from (4.5) that:
• The signal G {= 1 is generated when there are both signals in the given bit (ie, the transfer occurs at A = B = 1), so it is called the transfer ,
• the signal Р. = 1 allows the passage of the transfer C (. = 1 to the output, so it is called the propagation propagation function.
Using (4.5), we write down the expressions for the transport signals
(4.6)
(4.7)
Expressions (4.6) and (4.7) indicate that to obtain the transfer signals +, (i = 0, 1, 2,3) it is sufficient to have the functions G v P; (in fact, the input signals Ap B j bits of terms) and the external transfer signal C 0. They describe twostep combinational devices, in the first stage of which logical products are formed, and in the second  logical sums. Therefore, we can assume that the signals of all transfers will be formed simultaneously and for a shorter period of time than in the scheme of a multibit sequential adder with sequential transfer. The considered method of generating the transfers is called parallel, and the adders constructed by this method are sums with parallel transfer. Using the relations (4.6), (4.7), we can construct the scheme of the accelerated ( parallel) transfer for a 4bit adder.By combining the leads of C0 and C4 transfer of 4bit adders to a serial circuit, it is possible to build adders with a resolution of 8, 12, 16, etc. Such a multidigit adder is called a adder with sequential group transfer. To implement a parallel group transfer, we represent (4.7) in the form
(4.8)
where
(4.9)
Since the expressions (4.8) and (4.5) have the same structure, the parallel group transfer between the 4bit adder is performed in accordance with the expressions (4.6), (4.7), i.e. as well as the parallel transfer between the individual bits of each 4bit adder. In this case, signals (4.9) must be additionally generated in the transfer device for all of them. The accelerated transport scheme, constructed using the formulas (4.6), (4.7), (4.9), is shown in Fig. 4.5.
As can be seen from Fig. 4.5, the scheme of accelerated transfer with the help of the input signals C0, G r P (r = 0, 1, 2, 3) forms transfers to the upper bits C (C4, and generation functions G and propagation P of the hyphenation used for the group inclusion of 4bit adders.The generation of signals G v P. (i = 0, 1, 2, 3) and signal 5 (.the sum of two singledigit binary numbers is assigned to the shaper.) Figure 4.6 shows one of the possible variants of the shaper circuit.
In constructing this scheme, we used the identity
To prove it, we use the expression (4.1) and the formulas of the duality law (3.15):
The block diagram of a 4bit adder with accelerated transfer is shown in Fig. 4.7. The totalizer contains four identical generators (F0, F 1 , F2, F3) of separate digits of the sum of 5Р generation functions G; and propagation (see Figure 4.6), as well as an accelerated transfer scheme (see Figure 4.5), which generates, in addition to the translations C, C4, the generation functions G and propagation P for group transfer.
Fig. 4.5. Fast Transfer Scheme
Fig. 4.6. Shaper schema
Summationsubtractors of binary numbers. The scheme of a 4bit (including the sign discharge) addersubtracter containing four singledigit full adder and four exclusiveOR gates is shown in Fig. 4.8. The input of the addersubtracter receives two binary numbers, represented by 4bit additional codes and the Z mode setting signal. The value of Z = 0 corresponds to the addition mode, and Z = 1 to the subtraction mode. From the output of the addersubtracter, a 4bit additional result code , where is signed. The output of the transfer of the onedigit adder is not used. Exclusive OR elements are intended for input to singledigit bit summers В. inputs in the line (Z = 0) or inverse (Z = 1) form in accordance with Table. 4.3.
Table 4.3
Inputs 
Outputs 

Z 
B i 


0 
0 
0 

0 
1 
1 

1 
0 
1 

1 
1 
0 
For Z = 0, zero signals act on the inputs of the exclusiveOR gate, so the bit signals B t arrive at the inputs B. of all complete singledigit adders without inversion, at the input transfer C t of the first full adder, the signal is also zero. Therefore, the addition of two operands occurs.
Fig. 4.7. Scheme of a 4bit adder with accelerated transfer
With Z = 1, the exclusiveOR gates invert the bit signals B at the input of the transfer of the first complete singledigit adder C () = 1, resulting in an additional code of the subtrahend, therefore the subtraction operation is performed.
Fig. 4.8. The summationsubtraction circuit
thematic pictures
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