Multi-bit binary adder, Totalizer with sequential...

Multi-bit binary adder

The adder of this class performs the addition operation of two operands, each of which is an n-bit binary number. Two types of adders are used: sequential and parallel transfer combiners.

Totalizers with sequential transfer

In order to calculate the sum of two n-bit binary numbers, you can use incomplete and complete single-digit adder. In Fig. 4.4, a, b the scheme of the 4-bit adder and its symbol are given. The circuit is made up of four complete single-digit MS totalizers by connecting

Minimizing the structure of the formula for the total adder (a) and its logical schemes (b, c)

Fig. 4.3. Minimizing the structure of the formula for the total adder (a) and its logical schemes (b, c)

the output of the transfer of the previous one-digit adder with the transfer input of the subsequent one. Such an adder is called a adder with sequential carry. Using a zero-bit full one-bit adder extends the functionality of the 4-bit adder. The adder with sequential transfer has a low speed, since the sum signals S j

Scheme of a 4-bit adder with sequential carry (a) and its symbol (b)

Fig. 4.4. The scheme of a 4-bit adder with sequential transfer (a) and its symbol (b)

and carry C {+, at the output of the i-th single-digit adder appear after the transfer signal is generated in the previous ( i - 1) -th single-digit adder.

Totalizers with parallel transport

Let's consider a way of increase of speed on an example of a 4-bit adder. To do this, we write the output transfer signal (4.3) in the form



It follows from (4.5) that:

• The signal G {= 1 is generated when there are both signals in the given bit (ie, the transfer occurs at A = B = 1), so it is called the transfer- ,

• the signal Р. = 1 allows the passage of the transfer C (. = 1 to the output, so it is called the propagation propagation function.

Using (4.5), we write down the expressions for the transport signals



Expressions (4.6) and (4.7) indicate that to obtain the transfer signals +, (i = 0, 1, 2,3) it is sufficient to have the functions G v P; (in fact, the input signals Ap B j bits of terms) and the external transfer signal C 0. They describe two-step combinational devices, in the first stage of which logical products are formed, and in the second - logical sums. Therefore, we can assume that the signals of all transfers will be formed simultaneously and for a shorter period of time than in the scheme of a multi-bit sequential adder with sequential transfer. The considered method of generating the transfers is called parallel, and the adders constructed by this method are sums with parallel transfer. Using the relations (4.6), (4.7), we can construct the scheme of the accelerated ( parallel) transfer for a 4-bit adder.

By combining the leads of C0 and C4 transfer of 4-bit adders to a serial circuit, it is possible to build adders with a resolution of 8, 12, 16, etc. Such a multi-digit adder is called a adder with sequential group transfer. To implement a parallel group transfer, we represent (4.7) in the form




Since the expressions (4.8) and (4.5) have the same structure, the parallel group transfer between the 4-bit adder is performed in accordance with the expressions (4.6), (4.7), i.e. as well as the parallel transfer between the individual bits of each 4-bit adder. In this case, signals (4.9) must be additionally generated in the transfer device for all of them. The accelerated transport scheme, constructed using the formulas (4.6), (4.7), (4.9), is shown in Fig. 4.5.

As can be seen from Fig. 4.5, the scheme of accelerated transfer with the help of the input signals C0, G r P (r = 0, 1, 2, 3) forms transfers to the upper bits C (-C4, and generation functions G and propagation P of the hyphenation used for the group inclusion of 4-bit adders.The generation of signals G v P. (i = 0, 1, 2, 3) and signal 5 (.the sum of two single-digit binary numbers is assigned to the shaper.) Figure 4.6 shows one of the possible variants of the shaper circuit.

In constructing this scheme, we used the identity

To prove it, we use the expression (4.1) and the formulas of the duality law (3.15):

The block diagram of a 4-bit adder with accelerated transfer is shown in Fig. 4.7. The totalizer contains four identical generators (F0, F 1 , F2, F3) of separate digits of the sum of 5Р generation functions G; and propagation (see Figure 4.6), as well as an accelerated transfer scheme (see Figure 4.5), which generates, in addition to the translations C, -C4, the generation functions G and propagation P for group transfer.

Accelerated Transport Scheme

Fig. 4.5. Fast Transfer Scheme

Shaper Scheme

Fig. 4.6. Shaper schema

Summation-subtractors of binary numbers. The scheme of a 4-bit (including the sign discharge) adder-subtracter containing four single-digit full adder and four exclusive-OR gates is shown in Fig. 4.8. The input of the adder-subtracter receives two binary numbers, represented by 4-bit additional codes and the Z mode setting signal. The value of Z = 0 corresponds to the addition mode, and Z = 1 to the subtraction mode. From the output of the adder-subtracter, a 4-bit additional result code , where is signed. The output of the transfer of the one-digit adder is not used. Exclusive OR elements are intended for input to single-digit bit summers В. inputs in the line (Z = 0) or inverse (Z = 1) form in accordance with Table. 4.3.

Table 4.3




B i













For Z = 0, zero signals act on the inputs of the exclusive-OR gate, so the bit signals B t arrive at the inputs B. of all complete single-digit adders without inversion, at the input transfer C t of the first full adder, the signal is also zero. Therefore, the addition of two operands occurs.

4-bit adder scheme with accelerated carry

Fig. 4.7. Scheme of a 4-bit adder with accelerated transfer

With Z = 1, the exclusive-OR gates invert the bit signals B at the input of the transfer of the first complete single-digit adder C () = 1, resulting in an additional code of the subtrahend, therefore the subtraction operation is performed.

Summarizer-subtractor circuit

Fig. 4.8. The summation-subtraction circuit

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