Parallel registers - Informatics

Parallel registers

In parallel registers, writing and reading are performed in parallel code: when writing data, all the bits are simultaneously sent to register flip-flops, and when read, they are simultaneously output to an external device. Parallel registers have N information inputs X n and N outputs Y n (n = 0,1, 2, ..., N - 1), the input C {reads and the input C 2 readings. The main assignment of registers is the storage of information. In Fig. 3.28, a shows a scheme of a 4-bit parallel register containing four D-flip-flops and four logical elements of multiplication (AND).

The rules of the register for the general case are shown in Table. 3.11. The data is recorded by feeding the signal C, = 1 (C2 = 0) to the recording input, and reading the signal C 2 = 1 (C, = 0) to the read input. All bits of data are written and read at the same time.

Table 3.11


nth output
















With C, = C t = 0, the register triggers preserve the information (& frac34; -1 of the previous (k - 1) -step, the signals X * -1 on the inputs of the flip-flops can take the values ​​0 or 1 (symbol Φ), and the signals from their outputs do not pass through the coincidence circuit I. In the storage mode, signals with a zero level are taken from the n register's outputs Y AND-NOT in this mode, you can get a single level of output signals.

With C 2 = 0, C, = 1, the information is written to the register, the input signals X to ~ x ( n = 0, ..., N - 1) arrive

The scheme of the parallel register (a) and the state of the input data, register flip-flops and output data in the write and read modes (b)

Fig. 3.28. Parallel register scheme (a) and the state of the input data, register flip-flops and output data in write modes and reading (b)

into the triggers T0 - T N _ ,. In the write mode, zero-level signals are output from the Y outputs of the n register.

With C 2 = 1, C, = 0 the register goes into the read mode, the logical AND elements are opened, and then the signals stored in the flip-flops Q * -1 are read to the output of the register is Y k = Q k ~ { - Triggers T Q - T N, are in storage mode.

In the storage and readout modes, the state of the information inputs X n can be any (Φ = 0 or 1). Therefore, in these modes, you can set the input signals X n.

With C, = C 2 = 1, the register operates in asynchronous transfer mode (translation) of the input signals. In some cases, such a combination of input signals is forbidden.

In Fig. 3.28, b shows how the state of the inputs, flip-flops and register outputs changes in the write and read modes. The dark background reflects the change in the state of the register flip-flops during writing and the outputs when reading.

thematic pictures

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