Processor devices for dividing binary numbers, Operational...

The operating machine. Algorithm and hardware composition of OA

We assume that the division operation involves an 8-bit divisible and a 4-bit divisor . In Fig. 4.35 illustrates the algorithm for dividing the binary number A = 0010 00112 by the number S = 01112 (35: 7 = 5) using four registers and an adder. Registers RG i and RG 2 are used to store and shift the current value of the dividend , register RG 3 - storage of the additional code -B1 of the negative value of the divisor. The shift register RG fi serves to accumulate bits C j of the quotient. In the initial state, RG i and RG 2 are loaded with the divisible A, RG 3 - the additional code -B11 = 1001 (-7), a RG fi - zeros (see Figure 4.35).

At the r-th step of the algorithm, the addition operation is performed

where C4 j - transfer to the fourth digit; S 3 , S 2j S i , S 0 f is the sum or the i'th remnant.

The result of addition of C4 is y53 S 0. The output of the adder can be monitored in two ways:

• by the transfer value C4. in the fourth place, if C4 г = 0, then , otherwise ;

• By the value of the third digit S 3j sum, if S 3j = 1, then otherwise

As the condition X1 controlling the result of addition, we receive the transfer signal C4.

The actions at the r-th step of the algorithm for the operation of dividing binary numbers are determined by the value X 1 (see Figure 4.37).

1. If X1 (. = 0, then the value of the highest digits of the divisible ', therefore, the bit of the quotient Ci = 0.

The value of C j = X ij = O is written to the shift register RG i. Logical left shifting is performed one digit (towards the highest digits) of the contents RG i and RG 2 of the registers,

Fig. 4.35. Illustration of the principle of dividing binary numbers using four registers

the least significant bit in RG 2 is replaced by zero. At the next (r + 1) th step of the algorithm,

For X u = 0, the sum is not used at the output of the adder. In RG 1 is saved

2. If Xli = 1, then the value of the highest digits of the divisible ', therefore, the bit of the private C j - 1.

In this case, the sum is stored in RG v the value of the private C j = X lj = 1 is written in RG 2. Then the logical shift operation is performed to the left one digit (towards the higher digits) contents

RG 1 and RG 2. Thus, at the next (i + 1) -th step of the algorithm,

As can be seen from Fig. 4.35, five steps or cycles (r = 1, ..., 5) must be performed to obtain the four significant digits of the quotient, so we use a binary subtracting counter to connect to its outputs logical element of ZILI-NOT. If the number n = 510 = 1012 is written to the counter at the end of each cycle, then its contents are reduced by one after five cycles, then it will be empty (0002) after five cycles and a single signal will appear at the output of the ZILI-NOT, which we take as the second condition X 2.

The OA structure for dividing the binary numbers is shown in Fig. 4.36 Performed in the division of the micro-operation y - are given in Table. 4.15.

Table 4.15

As a result of combining micro-operations performed on the same time interval, we form the following micro-commands:

Fig. 4.36. Structural diagram of an operating machine for dividing binary numbers

where F1 is the microinstruction of the initial OA setting; F2 - microinstruction performed under condition X1. = 0; F3 - microinstruction performed under condition X1. = 1;

The following attributes are formed in OA (see Table 4.20):

• X1. - the result of comparing the current divisible

with a divider B. When the logical condition X1 is formed. = 0, with -Xli = 1;

• X2. - current state of the counter. At X2 (= 1, the counter is empty, the division operation is completed.

The

Logical Schematic OA is shown in Fig. 4.37. Consider the features of the hardware used.

Each of the ones shown in Fig. 4.37 registers RG v RG 2 and RG i has:

• four inputs for parallel loading of data and four outputs ';

• input D for sequentially writing one bit of data and shifting the contents of the register;

• control inputs Fh C, where the parallel load mode corresponds to the combination F = I1C = O, the sequential write and shift mode - F = O, C = 1.

The adder SM performs the function of comparing the values ​​of the four highest digits of the current divisor with the divider B at the i-th step of the algorithm and forming condition X1 .. To fix the comparison result, the signal C4 {is transferred to the fourth digit at its output. The current value of the divisible is fed to the inputs of the adder. and the additional code of the negative value of the divisor, and the sums 53 t S 2 t S Q are taken from the outputs. and the signal of the logical condition X r

The binary subtractive counter CT with the included ZILI-HE element ensures that the end of the division operation is fixed as a logical condition X 2 = 1. The counter has:

• Inputs D 2 , D v D q for the parallel loading of the number of cycles 510 = 1012;

• The clock input T to reduce the contents by one at the end of each cycle.

Fig. 4.37. The logic diagram of an operating machine for dividing binary numbers

To control the operation machine, you should:

• output Q3 of the register RG 2 is connected to the serial input D of the register RG V and the input D of the register RG 4 - to the output C4 of the adder, which will allow to realize the shift operations of the pair RG 2 -RG X in the direction of the highest digits at each step of the algorithm;

• Use four 2-ORI logical elements (see Figure 4.37). In this case, at Y x = 1, the high-order bits A 3 will enter the data inputs RG X < A 2 A X A 0 divisible, with C4 = 1 - signals S 3 S 2 S { S 0 from the output of the adder.

The control signals necessary for performing microinstructions are given in Table. 4.16. The diagram of OA control logic constructed on the basis of this table using Carnot maps (Figure 4.38) is shown in Fig. 4.37.

Table 4.16

 Microcommands and the condition X x Control signals RG 1 RG 2 RG 4 CT V C V C V C V T 0 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1

Fig. 4.38. Carnot maps for describing the logic of operating the automatic machine

The division operation can be implemented using two algorithms. Let's consider their features.

Algorithm 1. After loading the registers and the counter (micro-command Y,), the condition X, (transfer value C 4 at the output of the adder) is checked:

• If X, = 1, then the microcommand Y3 (RG t is loaded with the sum S 3 j52 gS u S 0 ra RG l - transfer C 4 = 1), after which the microinstruction V2 (successive load transfer C4 = X, to RG 3> the content shift RG., RG 2 and a decrease by one of the contents of the counter). Then, the condition X2 (counter CT) is checked. When X2 = 0 a new cycle starts, at X2 = 1 the operation is completed;

• If X, = 0, then the microcommand Y3 is skipped.

Algorithm 2. After loading the registers and the counter (micro-command Y,), the logical condition X2 (the contents of the CT counter) is checked:

• When X2 = 0, X1 is checked. If X4 = 1, then the microcommand Y3 is executed, after which the microinstruction Y2 and the cycle terminates. If Xj = 0, the microcommand Y3 is skipped;

• When X2 = 1, the operation is completed.

The curves in Fig. 4.39 graph-schemes of both division algorithms do not differ from similar graph-schemes of the operation of multiplication. Since the implementation of control

Fig. 4.39. Graphs of algorithms for the operation of dividing binary numbers

of automata is completely determined by the graph-scheme of the algorithm (albeit ambiguously), all the technical solutions considered in paragraph 4.4 can be used to control the operating automaton considered above.

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