Schema implementation of control memory
As a control memory, permanent memory devices are usually used. In the control memory, six 9-bit microprograms must be stored (see Table 4.14). Let us show for algorithm 2 that as a storage device (and, in fact, for forming) micro-programs, a combination scheme with three inputs and nine outputs, whose operation is described in Table 1, can be used. 4.14.
Fig. 4.31. Illustration of the principle of placing microinstructions in memory cells
Using the Carnot maps (Figure 4.32), we write down the structural formulas for the combination scheme
The scheme, constructed according to these structural formulas, is shown in Fig. 4.33. It has three address inputs ad 0,
Fig. 4.32. Carnot Maps for Combination Memory Scheme
Fig. 4.33. Storage for storage firmware
ad v ad 2, which receives a modified address from the BMU. The output of the combinational circuit is removed from the 3-bit address (AD 0 , AD v AD 2 ), the addresses of the firmware, the logical conditions checking signals (П, UX 2, ПХ,) and microinstructions (Y , Y 2 , Y 3 ).
Schematic implementation of the BMU
This block is used to modify the 3-bit address specified in the micro-command address field. The BMU (Figure 4.34) includes a counter made on three G-flip-flops and six AND elements, as well as a ZI-OR gate.
Each T-trigger has asynchronous inputs S and R, intended to be pre-set to the desired state. For S = I, R = 0, 1 is written to the trigger, for S = 0, R = 1 - 0, the combination 5 = 0, R = 0 corresponds to the storage mode. Address entry AD 2 AD 1 AD 0 in the counter is performed with clock pulses TI = 1 (clock pulse), when all logical elements of I are open. For example, if AD 0 = 1, then the asynchronous inputs of the trigger T 0 receive signals s = 1, A = 0 and at its output a signal ad 0 = 1.
Fig. 4.34. The firmware block
The ZI-OR logic element generates an output signal according to the following rule:
If the microinvision IIX1 or IIX2 is checked from the memory and the X1 or X2 value coming from the AP (see Figure 4.17) is equal to one, the address code at the BMU output is incremented by one:
Indeed, if the condition X1 is checked, i.e. Π = I, ΠXj = I, IIX2 = 0, and the signal X1 = 1 from OA, then the TI passes to the output of the SI-OR element according to the relation (4.18) and goes to the clock input of the trigger T 0 (ie T = TI), increasing the contents of the counter by one. A similar effect is achieved when checking the condition X2, i.e. Π = I, IlX1 = 0, ПХ2 = 1, when the signal X2 = I comes in.
In other cases, the TI does not pass through the ZI-OR element and the address entered in the counter is saved, i.e. acLad.acL = AD 2 AD i AD 0.
Note that the BMU scheme does not depend on the algorithm used, i.e. is the same for algorithms 1 and 2.
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