Storage devices, General information - Informatics

Storage devices

General

The individual devices of the complex of technical means that realize the memory function are called memory devices . In computing systems a wide set of memory is used, which is divided into separate classes, groups, types according to a number of distinctive features. Here are brief information about the main memory of the computer, which serves for recording, storing and issuing digital information in the process of its processing by the computer system.

For functional purposes, the memory is divided into two groups (see paragraph 1.5): operational and permanent memory.

According to the way information is stored, there are two types of RAM:

static RAM, in which the state of the memory elements while storing information remains unchanged. Static RAMs are built on transistors;

dynamic RAM, in which the state of memory elements (usually semiconductor capacitances) does not remain unchanged and requires a periodic process of regeneration (recovery) of the original signal levels.

The way to enter information in the ROM distinguish:

masked ROMs, in which jumpers in the drive are formed in the factory at the final stage of manufacturing memory chips;

programmable ROM in which the user has the option of using a special device (programmer) once implement burnout fusible webs, starting from their own program or code;

reprogrammable ROM, allowing multiple (hundreds and thousands of cycles) reprogramming.

One of the main characteristics of memory is memory capacity - the largest amount of data that can be simultaneously stored in memory. To quantify it, use a bit, a byte (8 bits), a computer word (16 or 32 bits). The speed can be characterized by the cycle time of recording or reading (sampling) of information and the time of access to the memory, which includes both cycles. To estimate the energy consumption, the specific power consumption (per 1 bit) is usually used. Two values ​​of specific power can be given: for storage and circulation.

Consider the simplest examples of the features of the construction and operation of static RAM and ROM.

Static RAM. The diagram of RAM is shown in Fig. 5.8. The structure of RAM includes:

• row decoders ( DCX ) and columns ( DCY ) that provide the choice of the required memory element (EI). Their inputs receive the M-bit address code A, and to the inputs DCX - Mx low-order bits of the code, to the inputs DCY - Mu of the highest digits. The number of outputs of the row decoder I = 2Mx, of the column decoder -J = 2 Mu. For the considered RAM Mx = Mu = 2 (M = 4), I = J = 4;

Static RAM Structure

Fig. 5.8. Static RAM Structure

• A drive represented as a matrix from memory elements (where i - line number ; a j - the column number, ), located along the lines i and the columns j. The column represents two bit lines and . EP is a bistable cell (flip-flop) made on two inverters (see paragraph 3.7). Transistor keys are intended to connect the trigger to the buses . The total number of EPs determines the information capacity of RAM, which is , where - number of lines, Is the number of columns, N = 16;

• a block of keys for fetching columns on transistor keys unlocking on the output signal DCY ;

• an input/output device containing recording and reading amplifiers, an inverter designed to receive direct and inverse signals when recorded, fed to the buses and two transistor switches K0, K1 - to connect an I/O device to the drive's bit lines;

• A control node consisting of logical elements. Static RAM has address inputs DI and outputs (direct and inverted), chip selection input (the crystal) , the recording resolution input is (or write/read) and the terminals for power supply.

The operating modes of the SOP are set by signaling according to Table. 5.2.

Table 5.2

Inputs

Exit

Modes

A

DI

DO

1

F

F

Z

Storage

0

1

A

1

Z

Record 1

0

1

A

0

Z

Record 0

0

0

A

F

D

Reading

In the storage mode the keys and are opened and the input/output device disconnected from the rest of RAM.

When the is received, the keys KO and Kl are closed. After sending the address code the signals Y = 1 and X 2 = 1 appear on the outputs of the decoders (signals on the other outputs are zero, this case is shown in Fig. 5.8). The signal X 2 = opens the transistor keys K0 2 j , K 2 j and the triggers of all EP2; line 2 (i.e. for all columns y = 0, 1, 2, 3) are connected to the bit lines of the SHPLH, LUPL. However, the signal Y, = 1 sets only two transistor keys KO, and K1, the column selection keys array, to the closed state. Therefore, only the flip-flop EP2 located at the intersection of line 2 and column 1 (SROP, WR1,) is connected to the input/output device.

When recording information ( W/R = 0), the input amplifiers are opened by the signal VW = 1, from their outputs to the bit lines ШР1, ШРО, direct and inverse the value of the input data DI. If DI = 0, then the signals on the bit lines ШРО, = 0, ШР1, = 1 and in the trigger of the memory element ЭП2, DI = 1 (WRO, = 1, WR1, = 0) will be written into the trigger 1.

When reading the information (W/R = 1), the output amplifiers are opened by the signal VR = 1. If the flip-flop EP2 stored 0, then on the bit lines SR0, = 0 1, and the outputs of the amplifiers take off the signals DO = 0, DO = <1> = 1. If the trigger has stored 1, then the signals on the indicated outputs have opposite values.

Persistent storage works only in storage and read-only modes. ROM drives also have a matrix structure. The functions of the EP are performed by semiconductor diodes or transistors (with fused jumpers) connected between the rows and columns of the matrix. The presence of a jumper corresponds, for example, to a logical unit, and its absence is zero. This provides non-volatile ROM, i. E. saving information when the supply voltages are disconnected. ROM chips have a dictionary organization, in which information is read in the form of a multi-bit code (words). The collection of memory elements in the storage matrix storing the word is called the memory cell. Each such memory cell has its own address. The number of EPs in a cell determines its bit depth N. If the number of address inputs M, then the number of cells is 2M, and the information capacity of the chip is 2 M ×. N bits. Thus, the common property of ROMs is their multi-bit (dictionary) organization, the reading mode as the main operating mode and non-volatile.

We will illustrate the property of energy independence and the operation principle of the ROM using Fig. 5.9, which depicts the simplest version of the circuit ROM, which uses semiconductor diodes. The read-only memory contains:

• a decoder DC with two addressable A 1 , A 0 inputs and four outputs forming the address lines ША00 - UIA11;

• five bit lines ШР4 - ​​ШР0;

• successive circuits composed of semiconductor diodes and fused jumpers (in the form of circles) and connected between address and bit lines;

• five light bulbs used to indicate the status of the ROM.

During programming, a part of the fused bridges is burned by passing an increased current through the diodes. As a result of programming in ROM, four 5-bit words are recorded, and the stored jumper corresponds to the logical unit level, and the burned jumper corresponds to the logical zero level. When the address code A 1 A 0 = 01 is applied to the input of the decoder, only a positive voltage appears on the address bus ША01, i.е. ША01 = 1. In those circuits where the jumpers are stored, the bulbs will light up

Circuit ROM using semiconductor diodes

Fig. 5.9. Diode Diode Circuit Diagram

and fix the level of the logical unit. In chains with unsaved bridges, the bulbs will not be lit, which corresponds to fixing the level of logical zero. It follows from Fig. 5.9, 5-bit code 01100 is read from the ROM in this case. Thus, the information (data) stored in the ROM is independent of the supply voltages, but is determined by the state of the fuse links.

Decoder (DeCoder - DC) is a combination device with M inputs and N outputs (M × N), converting the M -bit binary code to an N-bit unitary code with a single unit or a single zero. The maximum number of outputs N = 2 m corresponds to all possible sets of signals at the input of the decoder. Let's construct the scheme of the decoder DC, used in the above storage devices with the number of inputs M = 2, the description of which is specified by the truth table (Table 5.3). Using the table, we will write the structural formulas in the SDNF:

Table 5.3

k

Inputs

Outputs

0

0

0

0

0

0

1

1

0

1

0

0

1

0

2

1

0

0

1

0

0

3

1

1

1

0

0

0

Decoder 2 × 4

Fig. 5.10. 2 × 4 decoder

The logical scheme of the decoder 2 × 4, constructed according to the structural formulas, is shown in Fig. 5.10.

Flash memory. Flash memory can be considered as a logical development of constant memory, i.e. Memory, the main mode of operation of which is reading. Its appearance is conditioned by the desire of developers to create a non-volatile memory with RAM properties. Flash memory as an EEPROM memory, belongs to the class of nonvolatile read-write memory (NVRWM), but differs from it:

• Higher write speed, because the flash memory has a block structure and allows you to erase individual blocks. If at least one byte is changed, the whole block is read into the buffer, which contains the byte to be changed, the contents of the block are erased, the value of the byte in the buffer is changed, and then the block changed in the buffer is recorded. This technology reduces the write speed of small amounts of data to arbitrary areas of memory, but significantly increases the speed with consecutive recording of data in large portions;

• The lower cost of production, due to the simple organization of memory.

Due to low power consumption, compactness, durability and relatively high speed flash memory is now widely used in a variety of digital devices.

The device of a flash memory cell. The simplest cell of a flash memory is a metal-oxide-semiconductor structure or a MOS structure (Figure 5.11, a) containing:

• Control Gate, which performs its normal functions;

• Floating Gate, thanks to which the MOS structure has the ability to store binary information. By changing its state, 1 data bit is encoded. Usually, the presence of a charge on the gate corresponds to a logical zero, and its absence to a logical unit. In the initial state, the floating gate has no charge.

Consider the basic modes of operation of the flash memory cell [19].

Programming cells is the process of introducing electrons into the region of a floating gate by applying a voltage + E to the control gate (Figure 5.12, a).

The physical structure of the flash memory cell (a) and its symbol (b)

Fig. 5.11. Physical structure of the flash memory cell (a) and its symbol (b)

Programming Modes (a) and Erasing (b)

Fig. 5.12. Programming Modes (a) and erasing (b)

Reading modes when there is no (a) and there is (b) a charge on the floating gate

Fig. 5.13. Reading modes when there is no ( a ) and availability ( b ) charge on the floating gate

Erase mode. Removing a charge from a floating gate, or erasing the contents of a cell, is done by tunneling, while a high positive voltage + E 2 is applied to the source, control gate negative voltage -E 1. The electrons tunnel to the source (Figure 5.12, b).

Reading mode. In this mode, a positive voltage is applied to the control gate and the drain, and in the absence of a charge on the floating gate in the substrate between the source and the drain, a "channel is formed and a current appears (Fig. 5.13, a); if there is a negative charge, the channel is blocked and no current flows through the transistor (Figure 5.13, b).

thematic pictures

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