IC Compiler is the program deal from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the trunk end design of the very profound submicron designs. The inputs to the IC Compiler are: a gate-level netlist which may be from DC Compiler or third-party tools, a detailed floorplan which can be from prior Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by maker, and foundry-process data. IC Compiler produces a GDSII-format record as result ready for tape out of the chip. Furthermore, it is possible to export a Design Exchange Format (DEF) record of placed netlist data ready for a third-party router. IC Compiler runs on the binary Synopsys Milkyway databases, which may be used by other Synopsys tools based on Milkyway. 
4. 2 User Interfaces
IC Compiler can be utilized either with Shell software (icc_shell) or with Graphical user interface (GUI). Shell software is the command-line interface, which is employed for batch function, scripts, typing directions, and push-button kind of operations. Graphical user interface (GUI) can be an advanced graphical research and physical editing and enhancing tool. Certain tasks, such as very effectively displaying the design and providing visible analysis tools, can only performed from the GUI. Also tool control words (Tcl), which is utilized in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable strategies and scripts.
The IC Compiler design movement is an easy-to-use, single-pass circulation that provides convergent timing closure. Physique 4. 1 shows the essential IC Compiler design movement, which is centered around three central orders that perform location and optimization (place_opt), clock tree synthesis and optimization (clock_opt), and routing and postroute search engine optimization (way_opt). 
Figure 4. 1 - IC Compiler Design Stream 
For most designs, if the place_opt, clock_opt, and road_opt steps are followed, IC Compiler provides optimal results. You can use IC Compiler to successfully perform chip-level design planning, placement, clock tree synthesis and routing on designs with modest timing and congestion obstacles.
To further enhance the quality of results for your design you can use additional commands and switches for position, clock tree synthesis, and routing steps that IC Compiler provides.
1. Set up and make the libraries and the look data.
2. Perform design planning and ability planning.
-Design planning is to perform necessary steps to create a floorplan, determine the size of the look, create the boundary and central area, create site rows for the placement of standard cells, set up the I/O pads.
-Power planning, is to execute necessary steps to create a power plan to meet the electricity budget and the prospective leakage current.
3. Perform location and search engine optimization.
IC Compiler position and search engine optimization uses enhanced position and synthesis solutions to generate a legalized placement for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You can supplement this efficiency by optimizing for electric power, recovering area for location, minimizing congestion, and minimizing timing and design guideline violations.
To perform placement and search engine optimization, use the place_opt primary control (or from GUI choose "Placement" menu and then "Core Placement and Search engine optimization" sub-menu).
4. Perform clock tree synthesis and marketing.
To perform the clock tree synthesis and optimization period, use the order clock_opt (or
choose Clock > Key Clock Tree Synthesis and Search engine optimization in the GUI).
IC Compiler clock tree synthesis and inserted optimization solve complicated clock tree synthesis problems, such as blockage avoidance and the relationship between preroute and postroute data. Clock tree marketing enhances both clock skew and clock insertion wait by accomplishing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, hold off insertion, dummy insert insertion, and balancing of interclock delays.
5. Perform routing and postroute marketing.
To perform routing and postroute search engine optimization, use the way_opt core command word (or choose Course > Center Routing and Marketing in the GUI).
As part of routing and postroute search engine optimization, IC Compiler performs global routing, track assignment, fine detail routing, search and repair, topological optimization, and engineering change order (ECO) routing. For some designs, the default routing and postroute optimization setup produces best results. If required, you can supplement this functionality by optimizing routing patterns and minimizing crosstalk or by customizing the
routing and postroute marketing functions for special needs.
6. Perform chip finishing and design for making tasks.
IC Compiler provides chip finishing and design for production and yield capacities that you can apply throughout the many stages of the look flow to handle process design issues encountered during chip making.
7. Save the design.
Save your design in the Milkyway format. This format is the internal database format utilized by IC Compiler to store all the reasonable and physical information in regards to a design. 
4. 3 How exactly to Invoke the IC Compiler
1. Get on the UNIX environment with the user id and password.
The xterm unix fast becomes the IC Compiler shell command word prompt.
3. Start the GUI.
This home window can display schematics and logical browsers, among other activities, once a design is loaded.
4. 4 Preparing the Design
IC Compiler uses a Milkyway design library to store design and its own associated collection information. This section explains how to create the libraries, generate a Milkyway design library, read your design, and save the design in Milkyway format.
Setting Up the Libraries
Setting Up the energy and Ground Nets
Reading the Design
Annotating the Physical Data
Preparing for Timing Research and RC Calculation
Conserving the Design
4. 4. 1 Setting Up the Libraries
IC Compiler requires both logic libraries and physical libraries. The next sections explain how to create and validate these libraries.
IC Compiler uses reasoning libraries to provide timing and efficiency information for all those standard cells. In addition, logic libraries can offer timing information for hard macros, such as RAMs.
Lists the pathways where IC Compiler can locate the reasoning libraries.
Lists the logic libraries that IC Compiler can use to perform physical search engine optimization.
Lists the logic libraries that IC Compiler can search to solve references.
IC Compiler uses Milkyway research libraries and technology (. tf) records to provide physical library information. The Milkyway reference point libraries contain physical information about the typical cells and macro skin cells in your technology library. In addition, these reference point libraries define the location unit tile. The technology data files provide information like the brands and characteristics (physical and electro-mechanical) for each and every metal layer, which are technology-specific.
The physical catalogue information is stored in the Milkyway design library. For each cell, the Milkyway design collection has several views of the cell, which are used for different physical design tasks.
If you havent already created a Milkyway catalogue for your design (by using another tool that uses Milkyway), you need to make one utilizing the IC Compiler tool. If you curently have a Milkyway design collection, you must start it before focusing on your design.
Generate a Milkyway design library
To make a Milkyway design library, use the create_mw_lib demand (or choose Record > Create Catalogue in the GUI).
Open a Milkyway design library
To open a preexisting Milkyway design catalogue, use the open_mw_lib command word (or choose Data file > Open Library in the GUI).
Report over a Milkyway design library
To record on the research libraries attached to the design collection, use the -mw_reference point_library option.
To record on the products used in the design library, use the statement_units order.
Change the physical catalogue information
To change the technology data file, use the set_mw_technology_file command line (or choose
File > Set in place Technology Document in the GUI) to specify the new technology file name and the name of the look library.
Save the physical collection information
To save the technology or reference control information in a file for later use, use the
write_mw_lib_files control (or choose Document > Export > Write Library Record in the GUI). In one invocation of the demand, you can output only one type of file. To output both a technology record and a reference control document, you must run the command twice.
Consistency between your logic library and the physical catalogue is critical to achieving good results. Before you process your design, make sure that your libraries are regular by operating the check_catalogue command. 
4. 4. 2 Setting Up the Power and Ground Nets
By default, IC Compiler VSS as the ground online name. If you are using a different name,
you must designate the name by setting up the mw_logic0_net variable.
By default, IC Compiler uses VDD as the power net name. If you're using a different name, you must specify the name by setting up the mw_logic1_net changing.
4. 4. 3 Reading the Design
IC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC data files) format.
Reading a Design in Milkyway Format
Reading a Design in ASCII Format
4. 4. 4 Annotating the Physical Data
Reading the physical data from a DEF file
To read a DEF record, use the read_def command line (or choose Data file > Transfer > Read DEF in
icc_shell> read_def -allow_physical design_name. def
Reading the physical data from a floorplan file
A floorplan data file is a document that you previously created by using the write_floorplan
command (or by choosing Floorplan > Write Floorplan in the GUI).
icc_shell> read_floorplan floorplan_record_name
Copying the physical data from another design
To backup physical data from the design (CEL) view of 1 design in today's Milkyway design collection to another, use the backup_floorplan command (or choose Floorplan > Duplicate Floorplan in the GUI). 
icc_shell> backup_floorplan -from design1
4. 4. 5 Finding your way through Timing Examination and RC Calculation
IC Compiler provides RC calculation technology and timing evaluation capacities for both
preroute and postroute data. Before you perform RC calculation and timing research, you
Setup the TLUPlus files
You identify these files by using the set_tlu_plus_files command (or by choosing File
> Set TLU+ in the GUI).
icc_shell> arranged_tlu_plus_files \
-tech2itf_map. /avenue/map_file_name. map \
-max_tluplus. /course/worst_settings. tlup \
-min_tluplus. /course/best_settings. tlup
(Optional) Back-annotate wait or parasitic data
To back-annotate the design with delay information provided in a Standard Wait Format (SDF) data file, use the read_sdf command word (or choose Document > Transfer > Read SDF in the GUI).
To remove annotated data from design, use the remove_annotations control.
Arranged the timing constraints
At the very least, the timing constraints must include a clock definition for every clock sign, as well as type and output introduction times for each I/O interface. This requirement ensures that all signal paths are constrained for timing.
To read a timing constraints file, use the read_sdc command line (or choose Record > Transfer >
Read SDC in the GUI).
icc_shell> read_sdc -version 1. 7 design_name. sdc
Specify the analysis mode
Semiconductor device guidelines can vary with conditions such as fabrication process,
operating temps, and power voltage. The collection_operating_conditions command specifies the operating conditions for evaluation.
(Optional) Set the derating factors
If your timing collection will not include least and maximum timing data, you is capable of doing simultaneous bare minimum and maximum timing analysis by specifying derating factors for your timing catalogue. Use the set_timing_derate control to designate the derating factors.
Select the delay computation algorithm
By default, IC Compiler uses Elmore postpone calculation for both preroute and postroute wait calculations. For postroute wait calculations, you can opt for Arnoldi delay calculation either for clock nets only or for all those nets. Elmore delay calculation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi computation is best used for designs with smaller geometries and high resistive nets, but it requires more runtime and memory space. 
4. 4. 6 Cutting down the Design
To save the look in Milkyway format, use the save_mw_cel command line (or choose File > Save Design in the GUI). 
CHAPTER 5: Design Planning
5. 1 Introduction
Design planning in IC Compiler provides basic floorplanning and prototyping capabilities such as dirty-netlist handling, automated die size exploration, undertaking various functions with black package modules and skin cells, fast keeping macros and standard skin cells, packing macros into arrays, creating and shaping plan groupings, in-place search engine optimization, prototype global routing research, hierarchical clock planning, undertaking pin task on smooth macros and plan categories, carrying out timing budgeting, converting the hierarchy, and refining the pin assignment.
Power network synthesis and vitality network analysis functions, applied during the feasibility period of design planning, provide automatic synthesis of local power structures within voltage areas. Vitality network examination validates the energy synthesis results by accomplishing voltage-drop and electromigration evaluation. 
Figure 5. 1 - IC Compiler Design Planning 
5. 2 Responsibilities to be performed during Design Planning
Initializing the Floorplan
Automating Die Size Exploration
Handling African american Boxes
Performing an Initial Virtual Flat Placement
Creating and Shaping Plan Groups
Performing Ability Planning
Executing Prototype Global Routing
Performing Hierarchical Clock Planning
Performing In-Place Optimization
Performing Routing-Based Pin Assignment
Performing RC Extraction
Performing Timing Analysis
Performing Timing Budgeting
Committing the Physical Hierarchy
Refining the Pin Assignment
5. 3 Initializing the Floorplan
The steps in initializing the floorplan are defined below.
To load the top-level I/O pad and pin constraints, use the read_io_constraints demand.
To define the central and place the I/O pads and pins, use the initialize_floorplan command.
Use the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a set group of L, T, U, or cross-shaped web templates. These templates are being used to determine the cell boundary and shape of the central. To do this, use initialize_rectilinear_stop -form L|T|U|X.
To write top-level I/O pad or pin constraints, use the write_io_constraints command line.
Read the Synopsys Design Constraints (SDC) file (read_sdc demand) to ensure that signal pathways are constrained for timing.
To add cell rows, use the add_row demand.
To remove cell rows, use the slice_row order.
To save the floorplan information, use the write_floorplan command line.
IC Compiler is now able to write out the floorplan physical constraints for Design Compiler
write_physical_constraints -output result_file_name -port_side 
Figure 5. 2 - Floor Plan After Initialization 
5. 4 Automating Die Size Exploration
This section represents how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to ascertain smallest routable, die
size for your design while maintaining the relative placement of hard macros, I/O skin cells, and a power structure that satisfies voltage drop requirements. The technology is built-into the Design Planning tool through the estimation_fp_area control. The type is a literally flat Milkyway CEL view.
5. 5 Handling Dark Boxes
Black bins can be displayed in the physical design as either delicate or hard macros. A dark-colored container macro has a fixed height and width. A dark box soft macro sized by area and utilization can be designed to best fit the floorplan.
To deal with the black bins run the following set of commands.
set_qtm_technology -lib catalogue_name
create_qtm_port -type clock $port
write_qtm_model -format qtm_bb
5. 6 Performing an Initial Virtual Smooth Placement
The initial digital flat location is extremely fast which is optimized for line size, congestion, and timing.
The way to perform an initial online flat placement is explained below.
No straightforward requirements exist for analyzing the initial hard macro location. Measuring the grade of results (QoR) of the hard macro placement can be very subjective and frequently depends on sensible design experience.
Different methods can be use to control the preplacement of hard macros and increase the QoR of the hard macro placement.
Creating a User-Defined Array of Hard Macros
Setting Floorplan Location Constraints On Macro Cells
Placing a Macro Cell In accordance with an Anchor Object
Using a Virtual Level Placement Strategy
Enhancing the Tendencies of Virtual Washboard Placement With all the macros_on_border Switch
Creating Macro Blockages for Hard Macros
Padding the Hard Macros
To avoid positioning standard cells too near to macros, which can cause congestion or DRC violations, one can established a user-defined padding distance or keepout margin across the macros. One can set this cushioning distance over a selected macro's cell occasion master. During exclusive flat positioning no other skin cells will be located within the specified distance from the macro's edges. 
To place a cushioning distance (keepout margin) on the determined macro's cell instance grasp, use the set in place_keepout_margin control.
To place the hard macros and standard cells concurrently, use the create_fp_placement command.
IC Compiler does the next floorplan editing functions.
Undoing and redoing edit changes
Changing the way items snap to a grid
Aligning movable objects
5. 7 Creating and Shaping Plan Groups
This section identifies how to create plan categories for reasoning modules that need to be actually implemented. Plan groupings restrict the keeping cells to a particular region of the main area. This section also details how to automatically place and condition things in a design key, add cushioning around plan group boundaries, and stop signal leakage and keep maintaining signal integrity with the addition of modular stop shielding to plan groupings and very soft macros.
The pursuing steps are protected for Creating and Shaping Plan Communities.
To create an idea group, create_plan_organizations command.
To remove (delete) plan groups from the existing design, use the remove_plan_groups command.
Plan groups are automatically shaped, sized, and located inside the center area predicated on the distribution of cells caused by the initial online flat placement. Blocks (plan teams, voltage areas, and very soft macros) marked fix remain permanent; the other blocks, whether or not they are inside the primary, are subject to being changed or reshaped.
To automatically place and shape objects in the look core, shape_fp_blocks command line.
To prevent congestion or DRC violations, one can add padding around plan group
boundaries. Plan group padding places positioning blockages on the internal and external
edges of the plan group boundary. Internal padding is equivalent to boundary spacing in the key area. Exterior padding is equivalent to macro padding.
To add padding to plan teams, create_fp_plan_group_padding command.
To remove both exterior and internal padding for the plan categories, use the remove_fp_plan_group_padding command word.
When two signals are routed parallel to each other, signal leakage can occur between the signals, resulting in an unreliable design. One can protect sign integrity by adding modular stop shielding to plan categories and very soft macros. The shielding contains metal rectangles that are manufactured around the outside of the delicate macro boundary in the very best level of the design, and around the within boundary of the soft macro.
To add stop shielding for plan teams or tender macros, use the create_fp_block_shielding order.
To take away the indication shielding created by modular stop shielding, use the remove_fp_block_shielding control. 
5. 8 Performing Electricity Planning
After completed the design planning process and also have a whole floorplan, you can perform vitality planning, as explained below.
To define electricity and ground contacts, use the connect_pg_nets demand.
It is essential to add power and ground bands after doing floorplanning.
To add vitality and ground jewelry, use the create_rectangular_bands command.
To add electric power and earth straps, use the create_electricity_straps order.
To preroute standard cells, use the preroute_standard_cells command.
One is capable of doing floorplanning for low-power designs by employing power gating. Electric power gating gets the potential to lessen overall power usage substantially since it reduces leakage power as well as transitioning power.
As the design process moves toward creating 65-nm transistors, issues related to electricity and signal integrity, such as power grid era, voltage (IR) drop, and electromigration, have grown to be more significant and sophisticated. In addition, this complex technology lengthens the turnaround time needed to identify and fix power and signal integrity problems.
By performing power network synthesis you can preview an early on electric power plan that reduces the probability of encountering electromigration and voltage drop problems later in the thorough electric power routing.
To perform the PNS, one can run the set of following directions. 
Once the IR drop map complies with the IR drop constraints, you can run the commit_fp_rail
command to transform the IR drop map into a vitality plan.
Power network synthesis facilitates TLUPlus models.
set_fp_rail_strategy -use_tluplus true
Initially, when ability network synthesis first proposes a power mesh structure, it assumes that the energy pins of the mesh are linked to the hard macros and standard cells in the design. It then displays a voltage drop map that one can view to determine if it meets the voltage (IR) drop constraints. Following the electricity mesh is determined, one might discover "problem" areas in design because of this of automated or manual cell placement. These areas are referred to as chimney areas and pin connect areas.
To Check the PNS Integrity you can run the next set of commands.
set_fp_rail_strategy -pns_check_chimney_document pns_chimney_report
set_fp_rail_strategy -pns_check_pad_connection file_name
set_fp_rail_strategy -pns_check_hard_macro_interconnection file_name
One perform power network analysis to anticipate IR drop at different floorplan levels on
both complete and imperfect electricity nets in the design.
To perform power network analysis, use the analyze_fp_rail command.
To add virtual pads, use the create_fp_digital_pad command line.
To ignore the hard macro blockages, use the place_fp_power_plan_constraints demand.
When power and rail examination are complete, one can check for the voltage drop and electromigration violations in the look by using the voltage drop map and the electromigration map. You can save the results of voltage drop and electromigration current density beliefs to the database by keeping the CEL view that has just been analyzed.
To get a report of the existing principles of the strategies used by ability network synthesis
and ability network analysis utilizing the report_fp_rail_strategy order. 
5. 9 Performing Prototype Global Routing
One can perform prototype global routing to get an estimation of the routability and congestion of the design. Global routing is done to find possible congestion "hot areas" that might are present in the floorplan due to the keeping the hard macros or inadequate channel spacing.
To perform global routing, use the road_fp_proto demand.
5. 10 Performing Hierarchical Clock Planning
This section explains how to lessen timing closure iterations by carrying out hierarchical clock thinking about a top-level design through the early stages of the online flat movement, after plan groupings are manufactured and prior to the hierarchy is determined. One can perform clock thinking about a given clock net or on all clock nets in the look.
To set clock planning options, use the collection_fp_clock_plan_options command.
To perform clock planning businesses, use the compile_fp_clock_plan control.
To generate clock tree reviews, use the article_clock_tree command line.
Clock planning helps multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are linked through level-shifter cells. A level-shifter cell is a particular cell that can take signs across different voltage areas.
With this feature, clock tree synthesis can create a clock tree that honors the program groups while inserting buffers in the tree and stop new clock buffers from being located on top of a plan group unless they drive the entire subtree inside that particular plan group. This brings about at the least clock feedthroughs, making the design much easier to deal with during partitioning and budgeting. 
5. 11 Performing In-Place Optimization
In-place optimization can be an iterative process that is dependant on virtual routing. Three types of optimizations are performed: timing improvement, area restoration, and repairing DRC violations. These optimizations maintain the netlist's logical hierarchy as well as the physical locations of the skin cells.
To perform in-place search engine optimization, use the optimize_fp_timing order.
5. 12 Performing Routing-Based Pin Assignment
IC Compiler provides two ways to perform pin project: on delicate macros (traditional pin assignment) or on plan groupings (pin cutting flow).
To assign pin constraints, use the collection_fp_pin_constraints command.
To assign gentle macros pins, use the place_fp_pins demand.
To perform Stop Level Pin Assignmentuse, use the place_fp_pins -block_level command word.
To align smooth macro pins, use the align_fp_pins command.
To remove smooth macro pin overlaps, use the remove_fp_pin_overlaps command.
5. 13 Performing RC Extraction
Perform postroute RC estimation utilizing the extract_rc command word.
5. 14 Performing Timing Analysis
Use the survey_timing command to generate timing reviews for the look. With regards to the options selected, you can report valid pathways for the complete design or for specific paths. The timing article helps evaluate why some parts of a design may not be optimized.
5. 15 Performing Timing Budgeting
During the look planning level, timing budgeting can be an important part of obtaining timing closure in a bodily hierarchical design. The timing budgeting algorithm determines the corresponding timing boundary constraints for each top-level delicate macro or plan group (block) in a design. When the timing boundary constraints for every block are found when they are integrated, the top-level timing constraints are satisfied.
Timing budgeting distributes negative and positive slack between blocks and then creates timing constraints in the Synopsys Design Constraints (SDC) format for block-level implementation.
To create a pre-budgeting timing examination report file, use the check_fp_timing_environment control.
To run the timing budgeter, use the allocate_fp_costs command.
Immediately after budgeting a design, you can use the check_fp_budget_final result command to execute post-budget evaluation. 
5. 16 Committing the Physical Hierarchy
This section represents how to commit the physical hierarchy after finalizing the floorplan by changing plan groups to very soft macros. Committing the hierarchy creates a new level of physical hierarchy in the electronic toned design by creating CEL views for decided on plan teams. After committing the physical hierarchy, you can also "uncommit" the physical hierarchy by switching the soft macros back to plan teams.
In addition, this section also identifies how to propagate top-level preroutes into smooth macros, restore all pushed-down items in child skin cells to the top-level, and uncommit the physical hierarchy by switching soft macros back to plan organizations.
To convert plan groups to gentle macros, use the commit_fp_plan_categories command.
To push down physical items to the very soft macro level, use the thrust_down_fp_objects command.
To thrust up physical objects to the tender macro level, use the press_up_fp_objects command.
To uncommit the physical hierarchy, use the uncommit_fp_tender_macros order. 
5. 17 Refining the Pin Assignment
One can assess and evaluate the quality of the pin task results by examining the
placement of soft macros pins in the design and the pin position.
To check the keeping very soft macro pins, use the check_fp_pin_assignment command.
To check the pin alignment, use the check_fp_pin_position command. 
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