-triggers - Informatics

-triggers

The second way to eliminate the disadvantage of RS -triggers - the presence of a forbidden combination of input signals - leads to Jk-flip-flops. In Jk-flip-flop, the combination forbidden for RS -triggers is used

The T-trigger scheme, constructed on the basis of a two-stage synchronous RS-trigger (a), its conditional graphic designation (b) and timing diagrams illustrating the T-flip-flop function (in)

Fig. 3.22. Schematic T -The trigger, built on a two-stage synchronous RS -trigger (a), its conditional graphic designation (b) and timelines that illustrate the T -trigger function (in )

for useful purposes: with this combination of input signals, the Jk-flip-flop operates as a G-trigger.

JK-triggers can be constructed in two equivalent ways:

• based on two-stage synchronous R-triggers by creating conditions for the inverse (clocked) mode with a forbidden combination;

• Based on T-flip-flops by creating two additional inputs to control the state of the outputs.

Consider the first method, taking as a basis a two-stage synchronous RS -trigger. If in the first stage G, use NAND elements with three inputs, and additional inputs are used to organize feedbacks, as in the T-flip-flop, then after renaming the information inputs R, S to J , K we get the scheme of the JK-flip-flop, which is shown in Fig. 3.23, a. The conditional graphic designation of the JK-trigger is shown in Fig. 3.23, b.

With three combinations of input signals (J = K = 0;/= 1, K = 0 u J = 0, K = 1) The // (- trigger performs the RS functions of the trigger, i.e., the feedback does not affect its operation.

• With the combination J = K = 0, the signals S = are output from the outputs of logic elements 1 and 2 to the inputs of the first trigger, R corresponding to the storage mode;

The JK-trigger circuit (a), constructed on the basis of a two-stage synchronous RS-trigger, and its conditional graphic designation (b)

Fig. 3.23. Schematic JK -trigger (a), > (b)

• The combination J = 1, K = 0 for C = 1 corresponds to the recording mode 1. In this mode, the output of element 2 is formed signal R = 1. At the output of element 1, the signal depends on the previous state of the trigger. If the trigger is in the zero state Q = 0, then S = 0, since all inputs of element 1 receive single signals. In this case, a 1 is written to the trigger. If the flip-flop is in the single state Q = 1, then the signal Q = 0 is input to one of the inputs of the element 1. In this case, the trigger inputs T x, the signals S = R 1p therefore, the signal Q = 1

is stored at the output of the JK-

• The combination I = 0, K = 1 for C = 1 corresponds to the write mode 0 (reset). It is proved similarly to the recording mode 1.

With the combination/= K = 1, the JK-flip-flop performs the functions of the T-flip-flop. In this case, the J and K inputs of the flip-flop can be eliminated because single signals are applied to multiplication elements 1 and 2, and the JK flip-flop circuit degenerates into a T flip-flop circuit.

thematic pictures

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