IC Compiler is the program bundle from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the back end design of the extremely deep submicron designs. The inputs to the IC Compiler are: a gate-level netlist that can be from DC Compiler or third-party tools, a detailed floorplan that can be from past Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by maker, and foundry-process data. IC Compiler produces a GDSII-format data file as output ready for tape from the chip. Furthermore, you'll be able to export a Design Exchange Format (DEF) file of located netlist data ready for a third-party router. IC Compiler uses a binary Synopsys Milkyway data source, which is often employed by other Synopsys tools based on Milkyway. 
4. 2 Individual Interfaces
IC Compiler can be used either with Shell user interface (icc_shell) or with Graphical interface (GUI). Shell software is the command-line software, which can be used for batch mode, scripts, typing directions, and push-button type of operations. Graphical interface (GUI) can be an advanced graphical examination and physical editing tool. Certain duties, such as very accurately displaying the look and providing aesthetic analysis tools, can only just performed from the GUI. Also tool command word language (Tcl), which is employed in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable methods and scripts.
The IC Compiler design movement can be an easy-to-use, single-pass move that delivers convergent timing closure. Body 4. 1 shows the essential IC Compiler design stream, which is focused around three key orders that perform placement and search engine optimization (place_opt), clock tree synthesis and search engine optimization (clock_opt), and routing and postroute search engine optimization (road_opt). 
Figure 4. 1 - IC Compiler Design Stream 
For most designs, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler provides optimal results. You should use IC Compiler to proficiently perform chip-level design planning, positioning, clock tree synthesis and routing on designs with modest timing and congestion problems.
To further enhance the quality of results for your design you may use additional instructions and switches for positioning, clock tree synthesis, and routing steps that IC Compiler provides.
1. Setup and make the libraries and the design data.
2. Perform design planning and electricity planning.
-Design planning is to execute necessary steps to create a floorplan, determine the size of the look, create the boundary and central area, create site rows for the placement of standard cells, set up the I/O pads.
-Power planning, is to perform necessary steps to create a power plan to meet the power budget and the target leakage current.
3. Perform position and marketing.
IC Compiler placement and search engine optimization uses enhanced positioning and synthesis technologies to create a legalized positioning for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You may supplement this functionality by optimizing for vitality, recovering area for placement, lessening congestion, and minimizing timing and design guideline violations.
To perform placement and optimization, use the place_opt core demand (or from GUI choose "Placement" menu and then "Core Positioning and Optimization" sub-menu).
4. Perform clock tree synthesis and optimization.
To perform the clock tree synthesis and marketing phase, use the command line clock_opt (or
choose Clock > Core Clock Tree Synthesis and Marketing in the GUI).
IC Compiler clock tree synthesis and embedded marketing solve complicated clock tree synthesis problems, such as blockage avoidance and the correlation between preroute and postroute data. Clock tree marketing enhances both clock skew and clock insertion delay by carrying out buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, wait insertion, dummy load insertion, and balancing of interclock delays.
5. Perform routing and postroute optimization.
To perform routing and postroute search engine optimization, use the course_opt core command (or choose Option > Key Routing and Optimization in the GUI).
As part of routing and postroute optimization, IC Compiler performs global routing, detail routing, track assignment, topological marketing, and anatomist change order (ECO) routing. For some designs, the default routing and postroute search engine optimization setup produces maximum results. If necessary, you can complement this features by optimizing routing patterns and minimizing crosstalk or by customizing the
routing and postroute search engine optimization functions for special needs.
6. Perform chip finishing and design for processing tasks.
IC Compiler provides chip finishing and design for production and yield capabilities that you can apply throughout the various stages of the look flow to handle process design issues experienced during chip making.
7. Save the design.
Save your design in the Milkyway format. This format is the internal database format utilized by IC Compiler to store all the rational and physical information in regards to a design. 
4. 3 How to Invoke the IC Compiler
1. Log in to the UNIX environment with the user id and password.
The xterm unix quick becomes the IC Compiler shell order prompt.
3. Start the GUI.
This home window can screen schematics and reasonable browsers, among other things, once a design is loaded.
4. 4 Planning the Design
IC Compiler uses a Milkyway design collection to store design and its own associated catalogue information. This section details how to set up the libraries, build a Milkyway design library, read your design, and save the look in Milkyway format.
Setting Up the Libraries
ESTABLISHING the energy and Surface Nets
Reading the Design
Annotating the Physical Data
Preparing for Timing Analysis and RC Calculation
Keeping the Design
4. 4. 1 ESTABLISHING the Libraries
IC Compiler requires both reasoning libraries and physical libraries. The next sections summarize how to create and validate these libraries.
IC Compiler uses logic libraries to provide timing and operation information for everyone standard cells. Furthermore, logic libraries can offer timing information for hard macros, such as RAMs.
Lists the paths where IC Compiler can locate the reasoning libraries.
Lists the logic libraries that IC Compiler can use to perform physical optimization.
Lists the reasoning libraries that IC Compiler can search to resolve references.
IC Compiler uses Milkyway reference point libraries and technology (. tf) documents to provide physical catalogue information. The Milkyway research libraries contain physical information about the typical cells and macro skin cells in your technology catalogue. In addition, these research libraries define the position device tile. The technology data provide information like the brands and characteristics (physical and electrical power) for each metal layer, which can be technology-specific.
The physical library information is stored in the Milkyway design collection. For each cell, the Milkyway design catalogue includes several views of the cell, which are being used for different physical design responsibilities.
If you have never already created a Milkyway collection for your design (by using another tool that uses Milkyway), you will need to create one by using the IC Compiler tool. If you already have a Milkyway design collection, you must start it before working on your design.
Make a Milkyway design library
To make a Milkyway design library, use the create_mw_lib command line (or choose Record > Create Collection in the GUI).
Start a Milkyway design library
To open an existing Milkyway design catalogue, use the wide open_mw_lib demand (or choose Data file > Open Library in the GUI).
Report on the Milkyway design library
To article on the reference libraries mounted on the design collection, use the -mw_guide_library option.
To statement on the models used in the design collection, use the article_units order.
Change the physical collection information
To change the technology file, use the set in place_mw_technology_file command line (or choose
File > Set Technology File in the GUI) to specify the new technology record name and the name of the look library.
Save the physical collection information
To save the technology or guide control information in a file for later use, use the
write_mw_lib_files command line (or choose Document > Export > Write Catalogue Record in the GUI). In a single invocation of the demand, you can end result only one kind of file. To output both a technology document and a reference point control data file, you must run the control twice.
Consistency between the logic collection and the physical library is crucial to achieving good results. Before you process your design, make sure that your libraries are consistent by running the check_collection command. 
4. 4. 2 ESTABLISHING the energy and Earth Nets
By default, IC Compiler VSS as the bottom net name. If you're utilizing a different name,
you must specify the name by setting up the mw_reasoning0_net varying.
By default, IC Compiler uses VDD as the energy net name. If you are utilizing a different name, you must identify the name by setting the mw_reasoning1_net variable.
4. 4. 3 Reading the Design
IC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC data files) format.
Reading a Design in Milkyway Format
Reading a Design in ASCII Format
4. 4. 4 Annotating the Physical Data
Reading the physical data from a DEF file
To read a DEF document, use the read_def command word (or choose Document > Import > Read DEF in
icc_shell> read_def -allow_physical design_name. def
Reading the physical data from a floorplan file
A floorplan record is a file that you previously created by using the write_floorplan
command (or by choosing Floorplan > Write Floorplan in the GUI).
icc_shell> read_floorplan floorplan_document_name
Duplicating the physical data from another design
To duplicate physical data from the structure (CEL) view of 1 design in the current Milkyway design library to some other, use the backup_floorplan command word (or choose Floorplan > Duplicate Floorplan in the GUI). 
icc_shell> copy_floorplan -from design1
4. 4. 5 Preparing for Timing Research and RC Calculation
IC Compiler provides RC calculation technology and timing analysis capabilities for both
preroute and postroute data. Before you perform RC calculation and timing evaluation, you
Setup the TLUPlus files
You identify these files utilizing the set_tlu_plus_files demand (or by choosing File
> Set in place TLU+ in the GUI).
icc_shell> established_tlu_plus_files \
-tech2itf_map. /course/map_file_name. map \
-max_tluplus. /path/worst_settings. tlup \
-min_tluplus. /avenue/best_settings. tlup
(Optional) Back-annotate delay or parasitic data
To back-annotate the design with wait information provided in a Standard Delay Format (SDF) record, use the read_sdf command line (or choose Document > Import > Read SDF in the GUI).
To remove annotated data from design, use the remove_annotations demand.
Establish the timing constraints
At a minimum, the timing constraints must include a clock definition for each and every clock sign, as well as source and output arrival times for each and every I/O slot. This requirement means that all signal pathways are constrained for timing.
To read a timing constraints record, use the read_sdc command line (or choose Data file > Import >
Read SDC in the GUI).
icc_shell> read_sdc -version 1. 7 design_name. sdc
Designate the analysis mode
Conditions such as fabrication process, functioning temperature, and power voltage may differ semiconductor device parameters. You can designate the operating conditions for research with the set_operating_conditions command line.
(Optional) Set the derating factors
If your timing collection will not include minimum amount and maximum timing data, you is capable of doing simultaneous minimum and maximum timing evaluation by specifying derating factors for your timing catalogue. Use the place_timing_derate command line to designate the derating factors.
Select the delay computation algorithm
By default, IC Compiler uses Elmore delay calculation for both preroute and postroute hold off computations. For postroute wait computations, you can choose to use Arnoldi delay computation either for clock nets only or for any nets. Elmore wait computation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is best used for designs with smaller geometries and high resistive nets, but it needs more runtime and memory. 
4. 4. 6 Saving the Design
To save the look in Milkyway format, use the save_mw_cel command word (or choose Document > Save Design in the GUI). 
CHAPTER 5: Design Planning
5. 1 Introduction
Design planning in IC Compiler provides basic floorplanning and prototyping functions such as dirty-netlist handling, automatic die size exploration, doing various operations with black package modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and shaping plan teams, in-place search engine optimization, prototype global routing examination, hierarchical clock planning, performing pin assignment on smooth macros and plan communities, undertaking timing budgeting, switching the hierarchy, and refining the pin project.
Power network synthesis and electricity network analysis functions, applied during the feasibility phase of design planning, provide programmed synthesis of local vitality set ups within voltage areas. Electric power network evaluation validates the energy synthesis results by undertaking voltage-drop and electromigration research. 
Figure 5. 1 - IC Compiler Design Planning 
5. 2 Duties to be performed during Design Planning
Initializing the Floorplan
Automating Die Size Exploration
Handling Black color Boxes
Performing an Initial Virtual Flat Placement
Creating and Shaping Plan Groups
Performing Vitality Planning
Undertaking Prototype Global Routing
Performing Hierarchical Clock Planning
Performing In-Place Optimization
Performing Routing-Based Pin Assignment
Performing RC Extraction
Performing Timing Analysis
Performing Timing Budgeting
Committing the Physical Hierarchy
Refining the Pin Assignment
5. 3 Initializing the Floorplan
The steps in initializing the floorplan are explained below.
To weight the top-level I/O pad and pin constraints, use the read_io_constraints order.
To specify the primary and place the I/O pads and pins, use the initialize_floorplan command.
Use the initialize_rectilinear_stop command to create a floorplan for rectilinear blocks from a set set of L, T, U, or cross-shaped web templates. These templates are being used to look for the cell boundary and condition of the key. To get this done, use initialize_rectilinear_stop -condition L|T|U|X.
To write top-level I/O pad or pin constraints, use the write_io_constraints command line.
Read the Synopsys Design Constraints (SDC) data file (read_sdc demand) to ensure that all signal paths are constrained for timing.
To add cell rows, use the add_row command line.
To remove cell rows, use the lower_row demand.
To save the floorplan information, use the write_floorplan command word.
IC Compiler can now create the floorplan physical constraints for Design Compiler
write_physical_constraints -output output_file_name -interface_side 
Figure 5. 2 - Floor Plan After Initialization 
5. 4 Automating Die Size Exploration
This section details how to use MinChip technology in IC Compiler to automate the operations exploring and identifying the valid pass away areas to find out smallest routable, die
size for your design while preserving the relative keeping hard macros, I/O skin cells, and a power structure that meets voltage drop requirements. The technology is built-into the look Planning tool through the estimate_fp_area demand. The insight is a physically smooth Milkyway CEL view.
5. 5 Handling Black color Boxes
Black containers can be symbolized in the physical design as either very soft or hard macros. A dark field macro has a set elevation and width. A dark box gentle macro sized by area and utilization can be molded to best fit the floorplan.
To cope with the black boxes run the following set of instructions.
set_qtm_technology -lib library_name
create_qtm_dock -type clock $port
write_qtm_model -format qtm_bb
5. 6 Performing a short Virtual Smooth Placement
The initial electronic flat positioning is extremely fast which is optimized for wire duration, congestion, and timing.
The way to execute an initial online flat position is explained below.
No straightforward conditions exist for assessing the initial hard macro position. Measuring the grade of results (QoR) of the hard macro positioning can be quite subjective and often depends on sensible design experience.
Different methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro position.
Creating a User-Defined Array of Hard Macros
Setting Floorplan Position Constraints On Macro Cells
Placing a Macro Cell Relative to an Anchor Object
Using a Virtual Flat Placement Strategy
Enhancing the Behavior of Virtual Flat Placement While using macros_on_advantage Switch
Creating Macro Blockages for Hard Macros
Padding the Hard Macros
To avoid placing standard skin cells too close to macros, which can cause congestion or DRC violations, you can place a user-defined padding distance or keepout margin throughout the macros. You can establish this padding distance on a chosen macro's cell instance master. During online flat positioning no other skin cells will be placed within the given distance from the macro's edges. 
To arranged a padding distance (keepout margin) on the preferred macro's cell instance grasp, use the set_keepout_margin control.
To place the hard macros and standard cells concurrently, use the create_fp_positioning command.
IC Compiler does the next floorplan editing businesses.
Undoing and redoing edit changes
Changing the way things snap to a grid
Aligning movable objects
5. 7 Creating and Shaping Plan Groups
This section represents how to produce plan organizations for reasoning modules that require to be actually implemented. Plan categories restrict the placement of cells to a specific region of the core area. This section also details how to automatically place and condition objects in a design key, add padding around plan group boundaries, preventing signal leakage and maintain signal integrity by adding modular stop shielding to plan groupings and very soft macros.
The following steps are protected for Creating and Shaping Plan Groups.
To create an idea group, create_plan_groupings command.
To remove (delete) plan teams from the existing design, use the remove_plan_communities command.
Plan groupings are automatically molded, sized, and positioned inside the primary area predicated on the circulation of cells caused by the initial electronic flat position. Blocks (plan groups, voltage areas, and gentle macros) proclaimed fix remain predetermined; the other blocks, whether they are inside the core, are at the mercy of being migrated or reshaped.
To automatically place and condition objects in the look core, form_fp_blocks order.
To prevent congestion or DRC violations, you can add padding around plan group
boundaries. Plan group cushioning sets position blockages on the internal and external
edges of the program group boundary. Internal cushioning is the same as boundary spacing in the main area. External padding is equivalent to macro padding.
To add cushioning to plan organizations, create_fp_plan_group_padding control.
To remove both external and internal cushioning for the plan teams, use the remove_fp_plan_group_cushioning command.
When two signals are routed parallel to each other, signal leakage may appear between the signals, leading to an unreliable design. One can protect sign integrity by adding modular stop shielding to plan groups and gentle macros. The shielding involves steel rectangles that are created around the outside of the gentle macro boundary in the very best level of the look, and around the within boundary of the delicate macro.
To add block shielding for plan categories or tender macros, use the create_fp_stop_shielding command.
To remove the transmission shielding created by modular stop shielding, use the remove_fp_stop_shielding demand. 
5. 8 Performing Electric power Planning
After completed the look planning process and have an entire floorplan, you can perform power planning, as discussed below.
To define electric power and ground links, use the connect_pg_nets order.
It is necessary to add electricity and ground bands after doing floorplanning.
To add power and ground rings, use the create_rectangular_wedding rings command.
To add electricity and floor straps, use the create_vitality_straps order.
To preroute standard cells, use the preroute_standard_skin cells command.
One is capable of doing floorplanning for low-power designs by employing power gating. Electricity gating gets the potential to reduce overall power intake substantially because it reduces leakage electric power as well as transitioning power.
As the design process goes toward creating 65-nm transistors, issues related to electricity and signal integrity, such as electricity grid era, voltage (IR) drop, and electromigration, have become more significant and sophisticated. Furthermore, this complex technology lengthens the turnaround time needed to identify and fix vitality and signal integrity problems.
By performing electric power network synthesis one can preview an early on vitality plan that reduces the probability of encountering electromigration and voltage drop problems later in the specific ability routing.
To perform the PNS, you can run the set of following instructions. 
Once the IR drop map fulfills the IR drop constraints, one can run the commit_fp_rail
command to convert the IR drop map into a electric power plan.
Power network synthesis facilitates TLUPlus models.
set_fp_rail_strategy -use_tluplus true
Initially, when vitality network synthesis first proposes a ability mesh composition, it assumes that the energy pins of the mesh are linked to the hard macros and standard skin cells in the design. It then displays a voltage drop map that one can view to find out if it complies with the voltage (IR) drop constraints. Following the electricity mesh is dedicated, one might discover "problem" areas in design consequently of programmed or manual cell position. These areas are referred to as chimney areas and pin hook up areas.
To Check the PNS Integrity you can run the following set of orders.
set_fp_rail_strategy -pns_check_chimney_record pns_chimney_report
set_fp_rail_strategy -pns_check_pad_interconnection file_name
set_fp_rail_strategy -pns_check_hard_macro_connection file_name
One perform ability network evaluation to predict IR drop at different floorplan levels on
both complete and imperfect ability nets in the look.
To perform electricity network evaluation, use the analyze_fp_rail command line.
To add online pads, use the create_fp_online_pad command line.
To disregard the hard macro blockages, use the set_fp_power_plan_constraints command word.
When ability and rail examination are complete, one can check for the voltage drop and electromigration violations in the look utilizing the voltage drop map and the electromigration map. You can save the results of voltage drop and electromigration current density ideals to the data source by keeping the CEL view that has just been analyzed.
To get a report of the current worth of the strategies utilized by vitality network synthesis
and vitality network analysis by using the report_fp_rail_strategy command line. 
5. 9 Performing Prototype Global Routing
One is capable of doing prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to identify possible congestion "hot spots" that might are present in the floorplan because of the placement of the hard macros or limited channel spacing.
To perform global routing, use the option_fp_proto command.
5. 10 Performing Hierarchical Clock Planning
This section explains how to lessen timing closure iterations by performing hierarchical clock thinking about a top-level design through the early stages of the exclusive flat stream, after plan communities are manufactured and prior to the hierarchy is devoted. One can perform clock planning on a given clock net or on all clock nets in the design.
To established clock planning options, use the set_fp_clock_plan_options control.
To perform clock planning procedures, use the compile_fp_clock_plan control.
To generate clock tree reports, use the statement_clock_tree command word.
Clock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter skin cells. A level-shifter cell is a special cell that can bring alerts across different voltage areas.
With this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being put together with an idea group unless they drive the complete subtree inside that one plan group. This ends in a minimum of clock feedthroughs, making the design easier to control during partitioning and budgeting. 
5. 11 Performing In-Place Optimization
In-place optimization is an iterative process that is based on online routing. Three types of optimizations are performed: timing improvement, area restoration, and mending DRC violations. These optimizations protect the netlist's rational hierarchy as well as the physical locations of the cells.
To perform in-place marketing, use the optimize_fp_timing demand.
5. 12 Performing Routing-Based Pin Assignment
IC Compiler provides two ways to execute pin assignment: on delicate macros (traditional pin task) or on plan categories (pin cutting circulation).
To assign pin constraints, use the set in place_fp_pin_constraints command word.
To assign soft macros pins, use the place_fp_pins order.
To perform Stop Level Pin Assignmentuse, use the place_fp_pins -block_level control.
To align delicate macro pins, use the align_fp_pins command line.
To remove smooth macro pin overlaps, use the remove_fp_pin_overlaps control.
5. 13 Performing RC Extraction
Perform postroute RC estimation utilizing the extract_rc control.
5. 14 Performing Timing Analysis
Use the survey_timing command to create timing reports for the look. With regards to the options selected, one can report valid pathways for the whole design or for specific paths. The timing survey helps evaluate why some parts of a design may not be optimized.
5. 15 Performing Timing Budgeting
During the look planning level, timing budgeting is an important part of attaining timing closure in a bodily hierarchical design. The timing budgeting algorithm decides the matching timing boundary constraints for every top-level delicate macro or plan group (stop) in a design. When the timing boundary constraints for every single block are satisfied when they are executed, the top-level timing constraints are satisfied.
Timing budgeting distributes negative and positive slack between blocks and then generates timing constraints in the Synopsys Design Constraints (SDC) format for block-level execution.
To generate a pre-budgeting timing analysis report file, use the check_fp_timing_environment control.
To run the timing budgeter, use the allocate_fp_budgets command.
Immediately after budgeting a design, you may use the check_fp_budget_consequence command to execute post-budget research. 
5. 16 Committing the Physical Hierarchy
This section represents how to commit the physical hierarchy after finalizing the floorplan by switching plan teams to very soft macros. Committing the hierarchy creates a new degree of physical hierarchy in the online toned design by creating CEL views for determined plan groups. After committing the physical hierarchy, you can also "uncommit" the physical hierarchy by switching the smooth macros back into plan teams.
In addition, this section also identifies how to propagate top-level preroutes into gentle macros, retrieve all pushed-down things in child cells to the top-level, and uncommit the physical hierarchy by switching soft macros back into plan groupings.
To convert plan groupings to soft macros, use the commit_fp_plan_categories command.
To push down physical items to the tender macro level, use the press_down_fp_objects command line.
To push up physical objects to the delicate macro level, use the press_up_fp_objects control.
To uncommit the physical hierarchy, use the uncommit_fp_delicate_macros control. 
5. 17 Refining the Pin Assignment
One can assess and measure the quality of the pin assignment results by examining the
placement of tender macros pins in the look and the pin positioning.
To check the keeping delicate macro pins, use the check_fp_pin_project command.
To check the pin position, use the check_fp_pin_positioning command. 
Also We Can Offer!
- Argumentative essay
- Best college essays
- Buy custom essays online
- Buy essay online
- Cheap essay
- Cheap essay writing service
- Cheap writing service
- College essay
- College essay introduction
- College essay writing service
- Compare and contrast essay
- Custom essay
- Custom essay writing service
- Custom essays writing services
- Death penalty essay
- Do my essay
- Essay about love
- Essay about yourself
- Essay help
- Essay writing help
- Essay writing service reviews
- Essays online
- Fast food essay
- George orwell essays
- Human rights essay
- Narrative essay
- Pay to write essay
- Personal essay for college
- Personal narrative essay
- Persuasive writing
- Write my essay
- Write my essay for me cheap
- Writing a scholarship essay